Publications

2024

MICRO

Best Paper Runner-Up

A Mess of Memory System Benchmarking, Simulation and Application Profiling

Best Paper Runner-Up

Pouya Esmaili-Dokht, Francesco Sgherzi, Valeria Soldera, Isaac Boixaderas, Mariana Carmin, Alireza Monemi, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojković, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesus Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard

Publications

A Mess of Memory System Benchmarking, Simulation and Application Profiling

A Mess of Memory System Benchmarking, Simulation and Application Profiling

Processing in Memory: The Tipping Point

Processing in Memory: The Tipping Point

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems

Cost-Aware Prediction of Uncorrected DRAM Errors in the Field

Cost-Aware Prediction of Uncorrected DRAM Errors in the Field

STT-MRAM for Real-Time Embedded Systems: Performance and WCET Implications

STT-MRAM for Real-Time Embedded Systems: Performance and WCET Implications

Rethinking Cycle-accurate DRAM Simulation

Rethinking Cycle-accurate DRAM Simulation

PROFET: Modeling System Performance and Energy Without Simulating the CPU

PROFET: Modeling System Performance and Energy Without Simulating the CPU

DRAM Errors in the Field: A Statistical Approach

DRAM Errors in the Field: A Statistical Approach

Main Memory Latency Simulation: The Missing Link

Main Memory Latency Simulation: The Missing Link

Mainstream vs. Emerging HPC: Metrics, Trade-offs and Lessons Learned

Mainstream vs. Emerging HPC: Metrics, Trade-offs and Lessons Learned

HPC Benchmarking: Scaling Right and Looking Beyond the Average

HPC Benchmarking: Scaling Right and Looking Beyond the Average

Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators

Microbenchmarks for Detailed Validation and Tuning of Hardware Simulators

Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach

Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach

Main Memory in HPC: Do We Need More, or Could We Live With Less?

Main Memory in HPC: Do We Need More, or Could We Live With Less?

Enabling a Reliable STT-MRAM Main Memory Simulation

Enabling a Reliable STT-MRAM Main Memory Simulation

Large-Memory Nodes for Energy Efficient High-Performance Computing

Large-Memory Nodes for Energy Efficient High-Performance Computing

Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC

Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach

Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?

Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?

Limpio: LIghtweight MPI instrumentatiOn

Limpio: LIghtweight MPI instrumentatiOn

Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU

Energy Efficient HPC on Embedded SoCs: Optimization Techniques for Mali GPU

Measuring operating system overhead on CMT processors

Measuring operating system overhead on CMT processors

Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Characterizing the resource-sharing levels in the UltraSPARC T2 processor

Thread to strand binding of parallel network applications in massive multi-threaded systems

Thread to strand binding of parallel network applications in massive multi-threaded systems

Understanding the overhead of the spin-lock loop in CMT architectures

Understanding the overhead of the spin-lock loop in CMT architectures

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments

Optimal task assignment in multithreaded processors: a statistical approach

Optimal task assignment in multithreaded processors: a statistical approach

Thread assignment of multithreaded network applications in multicore/multithreaded processors

Thread assignment of multithreaded network applications in multicore/multithreaded processors

Towards resilient EU HPC systems: A blueprint

Towards resilient EU HPC systems: A blueprint

Evaluating memory efficiency in bioinformatics applications : a comprehensive performance study

Evaluating memory efficiency in bioinformatics applications : a comprehensive performance study

Impact of memory system characterization on high-performance applications

Impact of memory system characterization on high-performance applications

Minimun to Maximum : Evaluating Active Compute Memory through Min/Max Search Algorithm

Minimun to Maximum : Evaluating Active Compute Memory through Min/Max Search Algorithm

Active compute memory: enhancing memory and processing in near-memory architectures for vector classification

Active compute memory: enhancing memory and processing in near-memory architectures for vector classification

O(n) Key–Value Sort With Active Compute Memory

O(n) Key–Value Sort With Active Compute Memory

Reinforcement Learning-based Adaptive Mitigation of Uncorrected DRAM Errors in the Field

Reinforcement Learning-based Adaptive Mitigation of Uncorrected DRAM Errors in the Field

DRAM Errors and Cosmic Rays: Space Invaders or Science Fiction?

DRAM Errors and Cosmic Rays: Space Invaders or Science Fiction?

Citing Papers