Ramulator-Gate

At MICRO 2024, we published our paper on the Mess benchmark, showing how it can be used to evaluate the memory performance of real systems and simulators [1].

A year later, the Ramulator team published a preprint that characterized the Mess paper’s results and conclusions as incorrect due to “multiple trivial human errors” and “gross configuration errors” [2]. In 2026, this work was accepted to ISPASS [3]. The wording about “trivial” and “gross” errors was removed, but the main narrative remained.

We chose not to respond publicly to earlier preprints, despite what I consider serious misrepresentations of the Mess study. However, publication in an IEEE venue changes the situation.

In this series of posts, we will challenge several statements and results presented by the Ramulator team.

The first chapter of Ramulator-gate shows why better-looking results are not always the right results.

On one technical point, we agree with the Ramulator team: to resemble the bandwidth of the actual 8xDDR5-4800 Amazon Graviton3 and Intel Sapphire Rapids systems, Ramulator 2.0 requires a 16-channel DDR5-4800 configuration. With 8 channels, Ramulator 2.0 simulates roughly half of the expected bandwidth.

Where we disagree is whether the 16-channel Ramulator 2.0 configuration was obvious in this context.

This distinction matters.

The Ramulator team does not provide actual system measurements for the evaluated baseline and does not explicitly state that the baseline real systems are used to guide the simulator configuration. As a result, the 16-channel simulator configuration is presented in a way that appears more natural for an unspecified “ARM-based real system” than for Amazon Graviton3 with 8-channel DDR5-4800 main memory.

This is where narrative starts to diverge from the technical record.

And this is only the beginning.

In the next chapters, we will directly challenge the Ramulator team’s position that “channel” and “subchannel” are not distinct concepts in the DDR5 context.

Stay tuned!

DDR5 channels and sub-channels: Terminology matters

In the previous post, we saw that some memory simulators require 16 DDR5 memory channels to simulate actual 8-channel systems, such as Intel Sapphire Rapids and Amazon Graviton 3.

In the next two posts, I will explain why this happens.

It took us 10 months of email exchange with the Ramulator team to understand the technical reasoning behind this setup: channel and sub-channel terminology in DDR5 DIMMs.

A common understanding today is that a DDR5 DIMM is connected to the CPU through a DDR5 channel, which is partitioned into two sub-channels. In the HPC domain, which is the focus of our studies, this terminology is broadly used.

At the same time, some sources use a different convention: 1 DIMM = 2 channels.

To make things even more interesting, these two conventions are sometimes mixed within the same document.

My objective here is not to criticize these inconsistencies.

The documents discussed in this post cover everything from DDR5 chips to HPC servers, so it is understandable that terminology may vary. Also, the sub-channel concept was introduced with DDR5 DIMMs, so the community may simply need more time to converge on a consistent convention.

My objective is to point to a practical problem:

To prevent confusion, especially when the intended meaning differs from the mainstream convention, the term “DDR5 channel” should be defined explicitly.

In the next post, I will explain why this discussion is directly relevant to the Ramulator-gate saga.

Stay tuned.

It is OK to disagree. The question is what you do when you disagree.

In the previous post, we discussed DDR5 DIMM channel and sub-channel terminology, and the inconsistencies that appear across different sources.

The Mess paper followed the commonly used terminology: a DDR5 DIMM is connected to the CPU through a single DDR5 channel, which is partitioned into two sub-channels. This is also how Intel and Amazon describe the memory organization of the servers that we benchmarked.

Ramulator 2.0, however, assumes two channels per DDR5 DIMM. Although this is not the mainstream use of the term “channel”, this convention does appear in some documents, as discussed in the previous post. The Ramulator authors also expressed their view that channel and sub-channel are not two distinct concepts in the DDR5 context. We still find this interpretation difficult to reconcile with the terminology used by the other sources we have found.

This difference between the mainstream understanding and the Ramulator 2.0 convention explains why “Number of channels: 16” is needed to simulate actual 8-channel DDR5 systems.

It took us 10 months of email exchange with the Ramulator team to detect this issue.

Some people argue that detecting it should have been obvious.

We would argue that it is obvious only in hindsight.

This issue could have been solved with a clarifying comment on “DDR5 channel” in the Ramulator 2.0 configuration or README files.

This was our proposal for an easy way forward.

The Ramulator team, however, took a different path.

Despite knowing that our DDR5-channel reasoning followed a mainstream view in academia and industry, the Ramulator team publicly presented our channel configuration as a “trivial human error” and a “gross configuration error”.

The most striking part is that the Ramulator team also states that “the misconfiguration of the number of channels in DDR5 could have been easily resolved by emails and collegial discussions.”

Indeed.

That is exactly what we tried to do.

For 10 months.

And this is precisely where the record matters more than the narrative.