It's the Memory, Stupid!
Featuring Experts From
Join BSC, Intel and INESC-ID at MICRO 2026 for a half-day deep dive into memory system profiling and performance
analysis.
The tutorial is organized by the BSC Memory Systems Team, founded in 2014. Since its creation, the team has been actively
exploring memory systems for high-performance computing (HPC) and AI.
It has led multiple industrial projects with Huawei Technologies (China), Micron Technology (US and Italy), and Samsung Electronics (Korea).
The lecture on Roofline models will be delivered by experts
from the Heterogeneous Computing and Performance Modeling Hub created by INESC-ID, Lisbon. The lecturers have
developed multiple Roofline models, several of which are now used in
production tools for Intel HPC servers.
The TopDown analysis will be presented by an expert from
Intel with tens of years of experience in HPC application
profiling.
"In 1995, Wulf and McKee published a four-page note entitled Hitting the Memory Wall: Implications of the Obvious. The article projected the performance impact of the increasing speed gap between processors and memory, and predicted that, if the trends held, relative memory latencies would soon be so large that the processor would essentially always be waiting for memory — which amounts to hitting the wall."
"Technological evolutions and revolutions notwithstanding, the memory wall has imposed a fundamental limitation to system performance for 20 years."
Today, we are hitting the memory wall harder than ever — and most of us aren't even aware of it.
Previous Edition
Barcelona, February 2026
"It's the Memory, Stupid!" was also held as a full-day BSC training course at UPC Campus Nord, gathering over 100 participants. Its slides, reference papers and interactive visualizers remain openly available.
The Team
Lecturers & Organizers
Intel
Dr. Harald Servat
Software Enabling and Optimization Engineer
Harald Servat is an HPC system enthusiast with strong knowledge in monitoring systems, parallel programming models, compilers and computer architecture. He currently works at Intel Corp. on code modernization topics for the next generation of HPC systems (including CPU- and GPU-based systems). Harald got his PhD at BSC/UPC while researching fruitful combinations of instrumentation and sampling techniques to finely assess the code location and the associated performance inefficiencies in third-party applications.
Claudia Romo
CPU Performance Engineer
INESC-ID, Lisbon
Dr. Aleksandar Ilic
Associate Professor
Dr. Aleksandar Ilic is an Associate Professor at Instituto Superior Técnico, Universidade de Lisboa, and a Senior Researcher at INESC-ID. His research focuses on high-performance and energy-efficient computing, computer architectures, and heterogeneous systems.
Dr. Leonel Sousa
Associate Professor
Leonel Sousa received the Ph.D. degree in Electrical and Computer Engineering from Instituto Superior Técnico, Universidade de Lisboa, Portugal, in 1996. He is a Full Professor at Universidade de Lisboa and a Senior Researcher at INESC-ID. His research interests include parallel computing, computer architecture, and computer arithmetic. He has authored or co-authored over 300 publications and has organized major international conferences such as Euro-Par, FPL, and ARITH. He has been ACM Distinguished Speaker and IEEE Computer Society Distinguished Visitor. He is a Fellow of the IET, an ACM Distinguished Scientist, and an IEEE Computer Society Distinguished Contributor.
Alexandre Rodrigues
PhD Student
Alexandre Rodrigues is currently pursuing a Ph.D in Electrical and Computer Engineering from Instituto Superior Técnico, hosted by INESC-ID. His main research interests include high-performance computing, performance modelling, and its application to hardware-software co-design.
Barcelona Supercomputing Center
Dr. Eduard Ayguadé
Department Director
Computer Sciences
Eduard Ayguadé is full professor of the Computer Architecture Department at the UPC and director for research on Computer Sciences at the BSC. His research interests cover the areas of multicore architectures and vector accelerators, and programming models and compilers for high-performance architectures. He has published more than 400 publications in these topics and participated in several research projects (EU programmes or in direct collaboration with companies).
Dr. Petar Radojkovic
Group Leader
Memory Systems for HPC and AI
Petar Radojkovic has been with the Barcelona Supercomputing Center (BSC) since 2006. In 2014, he founded the Memory group, which explores memory systems for high-performance computing and AI. He has contributed to multiple European and industrial projects and served as principal investigator on collaborations with Huawei Technologies, Samsung Electronics, and Micron Technology, receiving several technology-transfer awards.
Dr. Xavier Martorell
Group Leader
Parallel Programming Models
Xavier Martorell is an Associate Professor at the Universitat Politècnica de Catalunya (UPC) and leader of the Parallel Programming Models group at the Barcelona Supercomputing Center (BSC). His research focuses on operating systems, programming models, compilers, and high-performance computing for heterogeneous architectures based on GPUs and FPGAs. He has contributed to national and European research projects and was a visiting scientist at the IBM T.J. Watson Research Center, where he participated in the development of system software for the BlueGene/L supercomputer. Martorell has co-authored over 85 publications, serves on the OpenMP Architecture Review Board, and actively supervises PhD students.
Pouya Esmaili-Dokht
Research Engineer
Memory Systems for HPC and AI
Pouya Esmaili-Dokht is the leading developer of Mess framework and a third year PhD student at the Universitat Politecnica de Catalunya (UPC), Spain. He earned his MSc degree in computer architecture at UPC in 2019. He is currently a Research Engineer in the memory systems team of Barcelona Supercomputing Center (BSC). He is collaborating with Micron Technology, Inc., on emerging near/in-memory architectures, memory system performance characterization and simulation.
Mariana Carmin
Research Engineer
Memory Systems for HPC and AI
Mariana Carmin is a Research Engineer and PhD Candidate at Barcelona Supercomputing Center. She earned her MSc degree in Computer Architecture from UFPR (Brazil) in 2022 and joined BSC shortly after. She is the lead developer of PROFET, focusing on the deep characterization of novel memory systems, workload profiling, and the development of analytical tools to predict performance on emerging memory systems.
Victor Xirau
Research Engineer
Memory Systems for HPC and AI
Victor Xirau is a Research Engineer working in memory systems profiling and hardware-software co-design. Since joining the team in 2023, he applies performance models like TopDown and Roofline, alongside tools such as PROFET and the Mess Framework, to analyze complex memory bottlenecks and inform hardware architecture decisions. His technical contributions to the group’s infrastructure include the development of the Mess 2.0 benchmark and the framework's integration with the BSC Tools ecosystem. Additionally, Victor is a Part-Time Lecturer for Operating Systems and Computing Infrastructures at La Salle Barcelona University.
Javier Beiro
Research Engineer
Memory Systems for HPC and AI
Javier Beiro joined the Barcelona Supercomputing Center in 2024 as part of the Memory group. He has contributed in several projects involving analysing memory systems performance through simulations, application profiling, performance prediction, and collaborating with Micron Technology studying the effect of processing-in-memory on AI Transformer models. As part of this research Javier has made several contributions such as creating assembly micro-benchmarks for Nvidia GPUs and addapting memory perfoncance benchmarks for the GEM5 infrastructure.
Pau Diaz
Research Engineer
Memory Systems for HPC and AI
Pau Diaz is a Research Engineer at the Barcelona Supercomputing Center (BSC). He earned his Bachelor’s degree in Electronic Engineering in Communications from La Salle Barcelona in 2025. Currently, he is pursuing a Master’s degree in Microelectronic Design at the Technical University of Catalonia (UPC). His work lies at the intersection of computer architecture and hardware evaluation, where he develops low-level benchmarks to characterize and optimize memory system performance.
Dr. Maria-Ribera Sancho
Head of Education
Education & Training
Dr. Maria-Ribera Sancho is a tenured professor at the Department of Service and Information System Engineering at UPC and Manager of Education and Training at Barcelona Supercomputing Center. She has been active in the Software Engineering field for over 25 years. She served as Dean of the Barcelona School of Informatics at UPC (2004-2010) and as vice-dean, head of studies in the same school (1998-2004). Her main research areas are learning analytics, conceptual modelling, information systems, software engineering, and Service Science Engineering (SSME). She has published extensively research articles and papers for International Congresses and Journals. She is member of the Information Modelling and Processing research group of the UPC and active at the innovation lab inLab leading learning analytics projects.
Supported by
The Facultat d'Informàtica de Barcelona (FIB) is one of the top 10 computer science schools in Europe. We have the resources, professors and experience to offer a wide range of courses.
The DARE project aims to boost European digital transformation by developing novel computing and AI technologies
EVITA is building a high-quality training framework for High-Performance Computing (HPC) and emerging technologies across Europe. EVITA connects leading institutions to deliver recognised qualifications and modular learning content that supports academia, industry, and innovation. Together, we’re shaping the future of HPC education.
At the Barcelona Zettascala Lab, our mission is to position Europe as a global leader in high-performance computing (HPC). Through innovation in advanced chip design, we aim to strengthen the continent’s technological sovereignty and foster a robust ecosystem encompassing both hardware and software.
International university campus offering studies in ICT Engineering, Architecture, Business, Digital Arts, Animation, Philosophy and Humanities and Health Engineering. Technology, artificial intelligence and innovation to face the challenges of today´s society.
ACAP advances open hardware design and the RISC-V ecosystem to strengthen technological sovereignty over processor IP. The project works on open HPC architectures, domain-specific accelerators, novel memory technologies, and the simulation and modelling methodologies needed to design them.
Schedule
Tutorial Agenda
Tutorial Programme
08:00h – 10:00h · Sessions to be announced
10:00h – 10:30h · Coffee Break
10:30h – 12:00h · Sessions to be announced
What You'll Gain
Learning Outcomes
Gain historical and technological insight into why the memory wall has persisted for more than 30 years — and why it's here to stay.
Understand the structure and behavior of modern memory systems and their impact on application performance.
Learn what to expect from key memory profiling tools — Roofline models, Mess framework, and CPI stacks — and how to interpret their results.
Receive pointers to advanced, publicly available materials for deeper exploration.
Be introduced to advanced topics in memory system design and efficient memory usage.
Before You Attend
Requirements
- A working knowledge of computer architecture and the memory hierarchy — the level assumed by the MICRO main programme
- Some familiarity with the Roofline model, Mess framework and CPI stacks is desirable but not mandatory
- A MICRO 2026 registration — the tutorial is open to all conference attendees at no extra cost
- No laptop or software setup required — the tutorial is lecture-based
Who Should Attend
Target Group
The MICRO community itself: computer architects, PhD students, postdocs and industry engineers who design, simulate, benchmark or profile memory systems. It is aimed at attendees whose architectures or workloads are bounded by memory rather than compute, and who want to know what today's profiling methodologies can and cannot tell them.
Where
Location
InterContinental Athenaeum Athens
Room to be announced
Syngrou Avenue 89-93
117 45 Athens, Greece
On-site only
Included in the MICRO 2026 registration. The exact room is announced with the conference programme.