Course recordings: It's the Memory, Stupid!
“It’s the Memory, Stupid!” aims to demystify memory systems for HPC and AI system designers and users.
For decades, memory performance has been one of the defining challenges in computer architecture. This was famously described by Wulf and McKee in their 1995 paper Hitting the Memory Wall: Implications of the Obvious. More than thirty years later, the memory wall is still with us, and memory systems have a major impact on the performance and cost of the HPC and AI systems we build. But some of the assumptions we make about memory deserve a closer look.
“It’s the Memory, Stupid!” aims to demystify memory systems for HPC and AI system designers and users.
The course analyzes memory-system performance through the lens of leading memory-performance analysis tools, presented by experts in the field.
Researchers from INESC-ID present Roofline models, including the Cache-Aware Roofline Model developed at INESC-ID.
The BSC Memory team presents memory performance through the interplay between memory bandwidth and latency. This view is at the heart of the Mess and PROFET tools, which have received several academic awards and supported collaborations with industrial partners including Samsung, Huawei, and Micron.
Intel presents Top-Down Microarchitectural Analysis, one of the most detailed approaches to performance analysis available today. It is widely used in high-performance computing to help users understand the microarchitectural factors that determine application performance.
Each lecture looks at performance from two sides: the characteristics of the target system and the behavior of the applications running on it. More importantly, it connects these two views. Since not everything can fit into one tutorial, we also provide pointers for those who want to explore the topics in greater depth.
The Same Elephant; Different Perceptions
Roofline models, Mess and PROFET bandwidth-latency analysis, and Top-Down Microarchitectural Analysis present different views of essentially the same problem, in the same room, on the same day. Therefore, it is also a useful lesson in intellectual humility and in accepting different analytical perspectives in research.
The lectures
- Lecture 1: Let’s Challenge a Few Assumptions
- Lecture 2: Roofline(s) — coming soon
- Lecture 3: Memory System Performance is Messy — coming soon
- Lecture 4: PROFET: No-stress Performance Prediction — coming soon
- Lecture 5: TopDown Microarchitecture Analysis — coming soon
- Lecture 6: Heterogeneous Memory Systems — coming soon
Thanks for being part of this!
A big thank you to the institutions and projects that supported this course:
- Universitat Politècnica de Catalunya
- La Salle – Ramon Llull University.
- DARE – Digital Autonomy with RISC-V in Europe
- EVITA – The EuroHPC Virtual Training Academy
- Barcelona Zettascale Lab
And to the people who made it happen: Harald Servat, Alexandre Rodrigues, Victor Xirau, Aleksandar Ilic, Leonel Sousa, Javier Beiro, Eduard Ayguade, Pau Diaz, Xavier Martorell, Toni Pena, Maria-Ribera Sancho, Pouya Esmaili-Dokht, Mariana Carmin, Jana Arabi, Miquel Moreto, Osman Unsal, Janine Gehrig, Romana Konjevod, and Ariadna Rodriguez. It is great to have you on board!